The design and manufacturing of electronic circuits, such as integrated circuits, includes synthesizing a logical representation of a circuit design into a physical implementation. Typically referred to as the implementation stage, physical synthesis includes placement and routing stages. During the placement stage, gates from a netlist of the circuit design are assigned to locations on a die area. In the routing stage, the wires that connect the various gates from the netlist are added. For the placement and routing stages, Electronic Design Automation (EDA) tools are typically used. EDA tools, a category of computer aided design (CAD) tools, are used by electronic circuit designers to create representations of circuit configurations, including representations of cells (e.g., transistors) and the interconnects (i.e., the data nets) that couple them together.
During the physical implementation, ramptime of data signals and clock signals in an electronic circuit is limited to meet signal integrity requirements and then checked during timing signoff. If a signal does not reach the rail before its next transition, then circuit functionality may be incorrect. Slow transitions can lead to higher power consumption as the transistor passes through the transition and can cause excessively high crowbar current, which has EM implication inside a cell (not checked at chip level) as well as delay and power estimate accuracy issues. Ramptime, also commonly referred to as slew, of signals must be within characterization range and meet maximum library characterization limits, otherwise delay prediction accuracy can be compromised.
If ramptime violations are found, corrections are made before proceeding in the design process. Current industrial EDA tools, like the IC Compiler (ICC) and PrimeTime® from Synopsys® of Mountain View, Calif., typically have limits in the library based on characterization limits that are fairly relaxed. Users typically set a global constant ramptime limit (CRL) to a more realistic constraint. A place-and-route tool and a timing signoff tool are examples of EDA tools that can employ a global CRL.
Employing the CRL during implementation and signoff can have multiple disadvantages including: making timing closure more difficult and time consuming, creating more of cross-talk strong aggressors, and creating more signal-EM violations. Additionally, using a CRL can penalize a slow clock domain with ramptime limits that are too aggressive for the data signals and clock signals (over-design), can make a need to waive every slow clock domain with ramptime violation or correcting false violations, can insert extra buffers to avoid false ramptime violations and can prompt the use of net length limits (like 400 nm, 500 nm) that may over-constrain strong drivers and have no impact on constraining weak drivers. Thus, while a CRL can provide a strict and sufficient limit, the CRL can be too conservative.